From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00 autolearn=ham autolearn_force=no version=3.4.4 X-Google-Thread: 103376,131ac66ded247fcc X-Google-Attributes: gid103376,public X-Google-Language: ENGLISH,ASCII-7-bit Path: g2news1.google.com!postnews.google.com!z14g2000cwz.googlegroups.com!not-for-mail From: "Suslik" Newsgroups: comp.lang.ada Subject: Re: Is there a translator from SPARK Ada to VHDL? Date: 23 Jan 2005 03:42:29 -0800 Organization: http://groups.google.com Message-ID: <1106480549.963006.322830@z14g2000cwz.googlegroups.com> References: <2e9040a1.0501201544.553ad2ac@posting.google.com> <1106284742.327319.93190@z14g2000cwz.googlegroups.com> NNTP-Posting-Host: 82.69.36.53 Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" X-Trace: posting.google.com 1106480554 3652 127.0.0.1 (23 Jan 2005 11:42:34 GMT) X-Complaints-To: groups-abuse@google.com NNTP-Posting-Date: Sun, 23 Jan 2005 11:42:34 +0000 (UTC) User-Agent: G2/0.2 Complaints-To: groups-abuse@google.com Injection-Info: z14g2000cwz.googlegroups.com; posting-host=82.69.36.53; posting-account=gYAXyg0AAACBz9MGbMix4w2s7RCrEplf Xref: g2news1.google.com comp.lang.ada:7941 Date: 2005-01-23T03:42:29-08:00 List-Id: Upkeep wrote: > Straightforward search in Google for "Ada VHDL translator" immediately > brings "Ada to Behavioral VHDL Translator" in many references. Yep, that's Sheraga's work. He did something similar with C too. The big problem is that behavioural VHDL (expressive, remarkably like Ada in syntax including a reasonable type system and iterative control structures) is not the same thing as synthesizable VHDL (very small subset, limited to reacting to signals on wires and updating state). And your VHDL must be synthesizable in order to load it onto an FPGA or produce an ASIC design. Since mapping from behavioural to synthesizable VHDL is very hard in the general case, you have a problem. (A secondary problem is that there is still not agreement on what VHDL is really synthesizable, although some progress has been made with a working group in this area). The eventual aim of the work I started on SPARK-to-VHDL was to provide a synthesizable VHDL implementation of SPARK programs. A key step is to route through the Pebble synchronous hardware description language which maps nicely onto synthesizable VHDL. You can choose to produce a pipelined implementation or a machine that executes SPARK pseudo-code. I also looked at how you can take a selected portion of a SPARK program, implement it in hardware, and replace its implementation with a handshaking interface to the hardware while still keeping the SPARK program description correct. More than (100 - 10^-4)% of people can conceivably want to know about this topic is described in the publications at http://www.suslik.org/Personal/publics.html which includes my PhD thesis. You might also want to have a look at what Neil Audsley and Michael Ward from York University have been doing on synthesizing legacy Ada (SPARK, if memory serves) into a state machine implementation on a PLD; the York Hardware Compiler, I believe. Hope this helps, Adrian