From mboxrd@z Thu Jan  1 00:00:00 1970
X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on polar.synack.me
X-Spam-Level: 
X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM
	autolearn=ham autolearn_force=no version=3.4.4
X-Google-Thread: 103376,131ac66ded247fcc
X-Google-Attributes: gid103376,public
X-Google-Language: ENGLISH,ASCII-7-bit
Path: g2news1.google.com!postnews.google.com!not-for-mail
From: happy_teddys@hotmail.com (Jim)
Newsgroups: comp.lang.ada
Subject: Re: Is there a translator from SPARK Ada to VHDL?
Date: 10 Feb 2005 10:03:46 -0800
Organization: http://groups.google.com
Message-ID: <2e9040a1.0502101003.3f46ce16@posting.google.com>
References: <2e9040a1.0501201544.553ad2ac@posting.google.com>
   <1106284742.327319.93190@z14g2000cwz.googlegroups.com>
 <1106480549.963006.322830@z14g2000cwz.googlegroups.com>
NNTP-Posting-Host: 134.130.112.38
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 8bit
X-Trace: posting.google.com 1108058627 10851 127.0.0.1 (10 Feb 2005 18:03:47
 GMT)
X-Complaints-To: groups-abuse@google.com
NNTP-Posting-Date: Thu, 10 Feb 2005 18:03:47 +0000 (UTC)
Xref: g2news1.google.com comp.lang.ada:8229
Date: 2005-02-10T10:03:46-08:00
List-Id: <comp.lang.ada>

"Suslik" <adi.google.@suslik.org> wrote in message news:<1106480549.963006.322830@z14g2000cwz.googlegroups.com>...
> Upkeep wrote:
> > Straightforward search in Google for "Ada VHDL translator"
> immediately
> > brings "Ada to Behavioral VHDL Translator" in many references.
> 
> Yep, that's Sheraga's work.  He did something similar with C too.
> 
> The big problem is that behavioural VHDL (expressive, remarkably like
> Ada in syntax including a reasonable type system and iterative control
> structures) is not the same thing as synthesizable VHDL (very small
> subset, limited to reacting to signals on wires and updating state).
> And your VHDL must be synthesizable in order to load it onto an FPGA or
> produce an ASIC design.  Since mapping from behavioural to
> synthesizable VHDL is very hard in the general case, you have a
> problem.  (A secondary problem is that there is still not agreement on
> what VHDL is really synthesizable, although some progress has been made
> with a working group in this area).
> 
> The eventual aim of the work I started on SPARK-to-VHDL was to provide
> a synthesizable VHDL implementation of SPARK programs.  A key step is
> to route through the Pebble synchronous hardware description language
> which maps nicely onto synthesizable VHDL.  You can choose to produce a
> pipelined implementation or a machine that executes SPARK pseudo-code.
> I also looked at how you can take a selected portion of a SPARK
> program, implement it in hardware, and replace its implementation with
> a handshaking interface to the hardware while still keeping the SPARK
> program description correct.

thank you for your reply. I think, that the Spark Ada isn't suitable
for hardware description, special for FPGA in safety critical systems,
because man must translates from Ada code into Pebble, then into VHDL,
in this procedure how can man assure that no errors of the code are
arisen? Furthermore why do you use Pebble? Why does man translate from
Ada direct into VHDL code, then  with the other synthesis tool
e.g.Xilinx WebPack write VHDL code in FPGA.?
 
I think, maybe Spark Ada is appropriate for the design of a complex
system(e.g. Hardware/Software co-design similar to SystemC) , very
safe language for the software desription.

Jim