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From: MatthiasR <MatthiasR@invalid.invalid>
Newsgroups: comp.lang.ada
Subject: Re: Forcing GNAT to use 32-bit load/store instructions on ARM?
Date: Sat, 26 Jul 2014 13:05:08 +0200
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Date: 2014-07-26T13:05:08+02:00
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Simon Clubley wrote:

> On 2014-07-20, MatthiasR <MatthiasR@invalid.invalid> wrote:
>>
>> So, if a C compiler is AAPCS-compliant, volatile bitfields should have
>> the desired behaviour. Whether a compiler is *really* AAPCS-compliant, is
>> another question. A well-known open source C compiler had bugs in this
>> area in several releases. Last year, attempts were made to repair it. I
>> don't know the current status.
>>
> 
> That open source C compiler wouldn't be called gcc by any chance
> would it ? :-)

How did you guess that? ;-)

> I did some experiments with using bitfields instead of bitmasks in
> some bare metal ARM target C code a couple of years ago and ran into
> the exact same problems as the OP's Ada code, with gcc's generated
> code using ldrb instead of ldr.

'strict volatile bitfields' are good keywords to find some informations 
about the bugs in this area - and the recent attempts to fix them.

> I haven't tried building a ARM cross compiler using the very latest
> versions of gcc however.
> 
> Simon.

It looks like there are indeed some changes in the latest versions: In
http://www.lpcware.com/content/forum/volatile-preventing-ldrb-byte-access
someone complains that the compiler does *not* use ldrb on a volatile 
struct...

Matthias