Re: Forcing GNAT to use 32-bit load/store instructions on ARM?

[Brian Drummond <brian@shapes.demon.co.uk>]

On Mon, 07 Jul 2014 17:38:54 -0500, Randy Brukardt wrote:

> "MatthiasR" <MatthiasR@invalid.invalid> wrote in message
> news:lpcck1$vtv$1@dont-email.me...

>> That is not really elegant, because records with representation
>> clauses, directly mapped onto hardware registers, look like the most
>> natural way to access these registers.
> 
> That *is* the most natural way to access those registers. But you can
> never access a *part* of a register, you always have to read or write
> the entire register at a time. Ada makes you make that explicit in your
> code, thus a temporary is required (pending new syntax).

There are exceptions to this. Some embedded CPUs (and even the old Z80) 
have atomic "bit test, set, clear" instructions. Where a register is 
represented in Ada as a packed array of booleans, setting one component 
of the array does actually compile down to a single "bit set" 
instruction. (I do not have a worked example with a record of packed 
booleans, but would expect the same).

(Except for bit 7 on the MSP430 gcc4.9 back end where you get a shift 
instead, which expands to about 30 instructions! Must report that one...)

But the bit access exception doesn't fundamentally change the argument : 
there are no access levels between the bit and the byte (or 32-bit word 
on some architectures) so there are no general hardware means for 
atomically accessing arbitrary sizes or alignments of record components. 

And thus, I see no way to coherently offer such facility in Ada with a 
guarantee of atomicity. 

One of Ada's strengths is that, however abstract the syntax and semantics 
may be, it is always close to the hardware in terms of the underlying 
operations it offers.

- Brian