Re: Forcing GNAT to use 32-bit load/store instructions on ARM?

[Simon Clubley <clubley@remove_me.eisner.decus.org-Earth.UFP>]

On 2014-07-11, Simon Wright <simon@pushface.org> wrote:
> Simon Clubley <clubley@remove_me.eisner.decus.org-Earth.UFP> writes:
>
>> On 2014-07-10, Simon Wright <simon@pushface.org> wrote:
>>> Simon Wright <simon@pushface.org> writes:
>>>
>>>> The x86_64 code accesses all 32 bits of V. If it is more efficient on
>>>> arm to access the relevant bytes for the component assignments, I
>>>> expect that's what would happen (as reported).
>>>
>>> Just tried this on Raspberry Pi (GCC 4.6.3): yes, it only accesses the
>>> relevant bytes.
>>
>> Just to make sure: you mean it uses ldrb/strb instead of ldr/str
>> in the generated code ?
>
> Yes. I don't understand all the asm, but that part is clear!
>
> _ada_atom:
> 	@ args = 0, pretend = 0, frame = 0
> 	@ frame_needed = 0, uses_anonymous_args = 0
> 	@ link register save eliminated.
> 	ldr	r2, .L2
> 	ldr	r3, .L2+4
> 	ldmia	r2, {r1, r2}
> 	str	r1, [r3, #0]
> 	ldrb	r1, [r3, #0]	@ zero_extendqisi2
> 	bic	r1, r1, #1
> 	strb	r1, [r3, #0]
> 	ldrb	r1, [r3, #3]	@ zero_extendqisi2
                         ^^^ 
Eeeek! :-)

That's an "interesting" variant I have not seen before.

It looks like gcc is generating code to do a byte offset load directly
from the top byte of the 32-bit word. In my bitfield struct experiments
in C I only ever saw gcc use ldrb when the bitfield was in the low
8 bits of the 32-bit word. I never managed to get gcc to do the above.

Congratulations on finding yet another variant to this. :-)

> 	bic	r1, r1, #128
> 	strb	r1, [r3, #3]
> 	str	r2, [r3, #0]
> 	bx	lr

Simon.

-- 
Simon Clubley, clubley@remove_me.eisner.decus.org-Earth.UFP
Microsoft: Bringing you 1980s technology to a 21st century world